It offers the flexibility of utilizing a wide variety of replacements algorithms if a cache miss occurs.The placement policy provides better cache hit rate.Fully associative cache structure provides us the flexibility of placing memory block in any of the cache lines and hence full utilization of the cache.Based on the Offset, a byte is selected and returned to the processor.If it doesn’t match, then it’s a cache miss and has to be fetched from the lower memory. If it matches, the block is present in the cache and is a cache hit. The Tag field of the memory address is compared with tag bits associated with all the cache lines.The eviction of memory block from the cache is decided by the replacement policy.If the cache is completely occupied then a block is evicted and the memory block is placed in that cache line.If the valid bit is 0, the new memory block can be placed in the cache line, else it has to be placed in another cache line with valid bit 0. The cache line is selected based on the valid bit associated with it.The cache organization can be framed as (1*m) row matrix. A memory block can occupy any of the cache lines. In a Fully associative cache, the cache is organized into a single cache set with multiple cache lines. Similarly, address 0x00FF(tag – 00_0000, index – 11_1111, offset – 11) maps to block 63 of the memory and occupies the set 63 of the cache.Īddress 0x0100(tag – 00_0001, index – 00_0000, offset – 00) maps to block 64 of the memory and occupies the set 0 of the cache. In the example, the tag bits are 6 (14 – (6+2)), which are stored in tag field to match the address on cache request.Īddress 0x0000(tag - 00_0000, index – 00_0000, offset – 00) maps to block 0 of the memory and occupies the set 0 of the cache.Īddress 0x0004(tag - 00_0000, index – 00_0001, offset – 00) maps to block 1 of the memory and occupies the set 1 of the cache. In the example, the index bits are 6 which are used to address the 64 sets of the cache. Index corresponds to bits used to determine the set of the Cache. In the example, the offset bits are 2 which are used to address the 4 bytes of the cache line. Offset corresponds to the bits used to determine the byte to be accessed from the cache line. The incoming address to the cache is divided into bits for Offset, Index and Tag. Since each cache block is of size 4 bytes, the total number of sets in the cache is 256/4, which equals 64 sets. Ĭonsider Main memory of 16 Kilobytes, which is organized as 4-byte blocks and Cache of 256 bytes with block size of 4 bytes. Every time a new memory is referenced to the same set, the cache line is replaced, which causes conflict miss.
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